Computer systems include a number of components and elements. Often the components are coupled via a bus or interconnect. Previously, input/output (I/O) devices were coupled together through a conventional multi-drop parallel bus architecture referred to as Peripheral Component Interconnect (PCI). More recently, a new generation of an I/O bus referred to as PCI-Express (PCIe) has been used to facilitate faster interconnection between devices utilizing a serial physical-layer communication protocol.
As devices and components become more complex and undertake heavier workloads, performance and power management have become increasing concerns. Part of the performance rests in the transfer speeds at the physical layer. The current PCI Express connector, which operates at 2.5, 5, and 8 GT/s to support Gen 1, 2, and 3 data links, respectively, may not be capable of supporting the 16 GT/s data rate that Gen 4, the future generation of PCIe seeks to achieve. Even with shorter channels, an investment in lower-loss board materials, and improved control of other channel elements, the connector could pose a barrier to Gen 4 implementation.
One data rate limitation is a pronounced resonance in the connector interface that manifests at roughly 8 GHz. This resonance causes frequency notches in the channel differential insertion loss, and corresponding peaks in return loss and lane-to-lane crosstalk that limit its use in a 16 GT/s channel. Several manufacturers produce PCIe connectors, so slight differences in this phenomenon may exist among them. It is understood that this general effect is present in many currently available products, since their basic geometry must conform to the PCIe Card Electromechanical Specification. Due to industry inertia and desire to maintain backward compatibility, it would be difficult to adopt a new high performance connector to supplant the current PCIe connector form factor. A backplane connector, for example, would preclude backward compatibility with current PCIe cards. Consequently, a method of suppressing the resonances in the current form factor is sought to improve data transmission at 16 GT/s.
Currently, with few exceptions, PCIe connector pins and add-in-card (AIC) terminal fingers are manufactured using identical geometry, even though some pins are assigned to high speed differential data lanes, some to lower speed clock lanes, and others to sideband signals, power, and ground. The ground pins adjacent to signals are physically no different from the signal pins, for example. For many pin positions the routing of the designated ground networks contributes to resonances by introducing unwanted reflections. Moreover, the resonance potentially causes crosstalk (e.g. inducement of current on an unintended conductor due to the electromagnetic field generated by driving current/signal on an intended conductor).